Speech analyzing system

ABSTRACT

1,236,431. Speech analysis. INTERNATIONAL BUSINESS-MACHINES CORP. 27 Aug., 1968 [7 Sept., 1967], No. 40821/68. Heading G4R. Sound analysing apparatus comprises a plurality of devices for detecting respective sound characteristics, means for scanning the devices in cycles, and storage means, the outputs of the devices being stored in the storage means under control of a system receiving an exponential timing signal. A speech signal is split by a preamplifier into high, middle and low frequency bands which go to a fricative selector, harmonic locator and envelope peak detector respectively. The envelope peak detector provides an automatic gain control voltage for the preamplifier, and detects the fundamental to start a scan ring and a timing ring. The scan ring enables ten cup-andbucket scan counters in turn to count pulses from the harmonic locator. The outputs of the fricative selector and scan counters are fed to interlocked balance units which compare them in pairs (adjacent) to detect formants. Adjacent outputs of the balance units are combined in pairs in and-invert units, the parallel outputs of which are entered into a column of a storage matrix, successive columns being selected in turn for this by the timing ring. The matrix contents are displayed on lamps. A fricative (or sibilant) sound can also start the timing ring but advance by more than one step is inhibited until the fricative has ended. Similarly, if the fricative occurs in the middle of a speech signal, so that the timing ring is already advancing, this advance is inhibited until the fricative has ended. An exponentially-falling voltage is used to control a multivibrator which drives the timing ring so that the intervals between successive steps of the ring increase exponentially. A fricative (or sibilant) sound resets the exponential voltage to its highest value so that following storing of the fracitive (consonant) characteristics in the matrix subsequent fine (vowel) details are also stored by virtue of the intial relatively short intervals between steps of the timing ring.

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SPEECH ANLYZING SYSTEM March 10, 1970` 15 Sheets-Sheet 1 Filed Sept. 7. 1967 AGENT March 10, 1970 G. l.. cLAPPr-:R 3,499,990

SPEECHANALYZING SYSTEM V Filed sept. v, 1967 15 sneetsfsheet z FIG. 20 FIG. 2b

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SPEECH ANALYZ ING SYSTEM Filed Sept. 7, 196'? 15 Sheets-Sheet 9 PREAMPLIFIER FIG. 3

` Mafcl'x l0, 1970 l?. CLAPPER 3,499,990

SPEECH ANALYZING SYSTEM Filed sept. 7. 1967 15 'sheets-sheet 1o FRlcATlve SELECTOR AND INVERT AINV GATED MULTIVIBRATOR March l0, 1970 G. L. CLAPPER 3,499,990

SPEECH ANALYZING SYSTE Filed Sept. 7, 196'? 15 Sheets-Sheet 11 ADJUSTABLE DELAY G M V 199 10K 1K D V 1K 2 02 -12v March 10, 1970 G. l.. cLAPPl-:R 3,499,990

sPEEH ANALY'ZING SYSTEM Filed sept. 7. 196'?u l 15 sheets-sheet 12 mm FIG. 12

El I OUT CIRCUIT 12V FIG' m |NVERTER FIG. 14

March 10, 197() G. L.. cLAPPER 3,499,990

sPEEcH ANALYZING SYSTEM r Filed Sept. 7, 1967 15 Sheets-Sheet 15 FIG. i6

SCAN COUNTER `SCC INTERLOCKED BALANCE UNITS FIG. I7

March l0, 1970 G. L, CLAPPER SPEECH ANALYZING SYSTEM 15 sheets-sheet 14 Filed sept. v, 19s? uNlvERsAL PULSE GENERATOR EVG 46s m FIG. 2O EXPONENTIAL VOLTAGE GENERATOR EMITTER FOLLOWER FIG. I8

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l5 Sheets-Sheet 15 UnitedStates Patent O 3,499,990 SPEECH ANALYZING SYSTEM Genung L. Clapper, Raleigh, N.C., assignor to International Business Machines Corporation, Armonk, N.Y., a corporation of New York Filed Sept. 7, 1967, Ser. No. 666,169 Int. Cl. G10l 1/00 U.S. Cl. 179-1 9 Claims ABSTRACT OF THE DISCLOSURE The present invention is concerned with speech analysis and utilizes a system employing a time transformation base of real time to a non-linear time base that essentially compresses information having uncertain time measurements. Formant transitions in speech, for example, tend to occur at widely separate time intervals for word endings but are rather consistent at the beginning of words. The extraction of information representing speech sounds over a linear time base results in an accumulation of information which includes unmeaningful data. The system also utilizes unvoiced sounds as time reference points providing a liner sampling resolution for voiced sounds following the termination of unvoiced consonants Moreover, the system lends itself to the encoding of fricative and sibilant sounds.

BACKGROUND Prior art speech analyzing systems utilize lencoding means predicated on a linear time measurement and sampling of speech waveforms and provide encoded data which contains considerable redundant information requiring costly storage facilities which render the systems highly uneconomical.

SUMMARY OF THE INVENTION The present invention is directed to a highly sophisticated speech analyzing system which eliminates the uncertainty that prevails as a result of frequency variations and provides for the storage of more meaningful data by excluding the uncertainties resulting from formant glides. This is achieved mainlyby a transformation of the linear time base to a non-linear time base which is unique in that an exponential function operates on a logarithmic form are utilized for expanding or contracting the total time interval and yet maintaining the property of linearly varying time increments. Sophistication in this technique is furthered by employing unvoiced sounds as the basis for time reference points, yielding finer sampling resolution for voiced sounds following the termination of unvoiced sounds.

The principal object of the invention is in the provision of a highly sophisticated voice analyzing system utilizing 'function and different portions of the exponential wavez a novel time transformation technique which results in the encoding of a greater amount of meaningful speech data than was possible by prior art systems.

Another object is to provide a system which eliminates less meaningful speech data to provide greater economy in the coding and storage of the meaningful data.

A specific object resides in the applicationof a novel ice` to yield finer sampling resolutions for the encoding of speech sounds.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

DESCRIPTION OF THE DRAWINGS FIG. 1 is an over-all configuration representating the present invention.

FIG. 2 shows how FIGS. 2a through 2f are assembled to represent a detailed configuration of the invention.

FIG. 3 shows the details of a preamplifier.

FIG. 4 shows the details of a harmonic locator.

FIG. 5 shows the details of an envelope peak detector.

FIG. 6 shows the details of a fricative selector.

FIG. 7 shows the details of an AND invert.

FIG. 8 shows the details of a matrix latch.

FIG. 9 shows the details of an adjustable delay.

FIG. 10 shows the details of a gated multivibrator.

FIG. l1 shows the details of a ring drive.

FIG. l2 shows the details of ring units.

FIG. 13 shows the details of an OR circuit.

FIG. 14 shows the details of an inverter.

FIG. 15 shows the details of a delay switch.

FIG. 16 shows the details of a scan counter.

FIG. 17 shows the detail of an interlocked balance unit.

FIG. 18 shows the details of an AND-emitter follower.

FIG. 19 shows the details of a universal pulse generator.

FIG. 20 shows the details of an exponential voltage generator.

FIGS. 21a, 2lb, 21C and 21d are a series of plots illustrating the advantages derived from the time transformation concept.

FIG. 22 shows multivibrator characteristics, voltage and time parameters.

In its broadest aspects the system, as seen in FfIG. l, lcomprises a speech analyzer SPA, a storage matrix SM, a scan ring SCR, a non-linear time base and interlock TB&I, an output pattern display and. various manual controls including a microphone 1. To prepare the system for operation, the RESET button is depressed follo-wed bythe `depression of the TALK button. Speech input is thereafter admitted to the system via microphone 1 which transforms the speech sounds into various waveforms that enter the speech analyzer SPA by way of lines 25, 26'and 51. The speech analyzer under control of scanning signals SCO1-SCO10, issued by scan ring SCR, provide l1 different speech measurements H1-H11 which are suitably coded and passed into the storage matrix SM under `control of timing signals TUa through TUe issued by the time base TB&I. The storage matrix is of a well-known coordinate type constituted of the storage matrix latches arranged in columns and rows.

The manner in which the salient features of the invention are performed will be described in detail hereinafter following the detailed descriptions of the important components constituting the invention.

DESCRIPTION OF COMPONENTS Speech pre-amplifier The speech pre-amplifier PA, shown in FIG. 3, includes input lines 2 and 3 with the former connected to an RC network 4 terminating with a Sensitivity control K means 5 in turn connected between ground and a -6 volt supply. Line'3 is connected to the emitter 7e of a transistor 7, the base 7b and collector 7c thereof being resistively coupled to the network 4. rll`he emitter 7e is also connected to ground and the collector 7c `is resistively coupled to a -12 volt supply. A grounded capacity network 6 acts as an electrical noise filter to isolate the pre-amplier rst stage. The output of the transistor 7 is couple-d by way of line 8 and capacitor 9 to the base 10b of transistor 10. The base 10b is also resistively coupled to collector 10c of the transistor 10. The emitter 10e is connected to ground by way of a diode 11 and also to an RC filter network 12. Similarly, the emitter 14e is connected to ground by way of diode 13 and to network 12. The base 14b of the transistor 14 is capacitively coupled by 'way of line 15 to the output line 16 extending from the transistor 10. The base via line 15 is resistively coupled to an output level control means 17 connected between ground and a -12 volt supply. This output is also capacitively coupled by way of line 18 which is also connected to an output line 19 extending between the collector output of transistor 14 and the base 20b of transistor 20. The line 18, including capacitor 18', serves as a degenerative coupling which is effective at low frequencies of about l5 c.p.s. to provide stabilization. Transistor 20 has its collector grounded and the emitter 20e resistively coupled to a -12 volt supply and also to an output network consisting of lines 23, 24 and 25. An automatic gain control signal AGC, line 26 extends from the envelope peak detector EPD and joins the RC network 12 at a point 27, whereby a wider range of control is exercised by virtue of the fact that the AGC signal is impressed across the two successive stages, namely transistors 10 and 14, to provide smoothed outputs for automatic gain control and harmonic analysis. The pre-amplifier PA thus provides, under control of the AGC signal, a high frequency output on line 23 which contains the high frequency noise-like components for operation in the fricative selector; an output on line 24, constituting a middle range of frequencies from 250 cycles per second to 3000 cycles per second for operating the harmonic locator HL; and an output on line which contains only the low frequency components for operating the envelope peak detector EPD.

Fricative selector The fricative selector shown in FIG. 6 comprises essentially three transistors 100, 106 and 108 and an LC network 103. Input signals of high frequency noise-like characteristics are applied by way of line 23, extending from the pre-amplifier PA to the base of transistor 100. The emitter of transistor 100 is resistively coupled to a -12 volt supply and also by way of line 101 to the base of transistor 106. The collector of transistor 100 is coupled to ground and to the base of transistor 108 by way of lines 102 and 103 and a capacitor 103C. The inductor of 2.5 mh. is connected across lines 103 and 101. The emitters of transistors 106 and 108 are connected by line 107 in turn resistively `coupled to a -6 -volt supply. The collector output of transistor 108 is connected to a +12 volt supply by way of line 109 and also to the base of transistor 116 by way of paths 110 and 112 with a capacitor 111 connected therebetween. Also connected between line 112 and a -6 volt supply is a network 113 which includes a transistor 114 and a diode 115. The emitter of the transistor 116 is resistively coupled by way of line 119 to a potentiometer 120 in turn connected to an output line 121. The collector of the transistor is connected to a grounded line 117 in turn coupled by way of capacitor 118 to the potentiometer 120.

The transistor 100 serves as a driver while transistors 106 and 108 in combination serve as a difference amplifier with the LC network 103 providing a delay. The output from the fricative selector FS, on line 110, consists of high frequency noise-like signals above 4 kc. The rectifying network comprising network 113 and transistor 116 provides a DC level which is proportional to the peak to peak signals presented to the input network 113.

Harmonic locator The harmonic locator HL, shown in FIG. 4, comprises a peak locator 28 and a univibrator 39, the former determining points of peak amplitude and the latter standardizing the output pulse. The peak locator 28 includes a pair of transistors 30 and 37 connected in the manner shown. Input to the transistor 30 is from the line 24 through a transistor 29 in turn connected to base 30b of the transistor 30. Collector 30e is coupled to ground by way of a resistor 31 and emitter 37e of transistor 37 interconnected to ground by way of a capacitor 32. The output from emitter 30e is coupled through diode 33 to a point A in the circuit path connected to emitter 37e. The base 37b of transistor 37 is coupled to a point B situated in the path between diode 34 and a resistor 35 terminating at a 12. volt supply. The output from the collector 37C which represents the output of the peak locator 28 extends through a line 38 connected to base 40b of transistor 40 which is the input to the univibrator 39. The transistor 40 has its emitter 40e connected to a -6 volt supply and the collector 40e connected to a +6 volt supply by way of line 41 and a load resistor. From a point E a path 42 including a capacitor 42 proceeds to the base 45b of a transistor 45. From a point F in this path a width adjustment potentiometer 44 is connected through a line 43. The emitter 45e is connected to a -12 volt supply by way of a line 46, and the collector 45t,` of the transistor 45 is connected by way of line 47 to a +6 volt supply and to an output line 48 which is grounded by means of a diode 49. A feedback path 50 including a resistor 51 interconnects the output line to the base of transistor 40.

In the operation of the harmonic locator the input speech waveform is limited to a peak to peak amplitude of about two volts. Points of peak amplitude are determined by the novel peak locator circuit combined with a univibrator for output pulse standardizations. On the first large positive peak of the pitch period representing the fundamental excitation, transistor 30 acts as an emitter follower lpower driver to charge capacitor 32 through the diode 33. This will drive point A to its most positive value, about +2 volts. Simultaneously, transistor 30 drives point B through the diode 34 to the same voltage level. Thus, during positive slopes of the complex waveform, no appreciable voltage difference appears between polnts A and B, as a result of which transistor 37 does not conduct, points C and D are maintained near -12 volts, transistor 40 is cut off, point E is held at +6 volts and point F at about -12 volts. Current iiows from the width adjustment potentiometer 44, through a 20K resistor in the line 43, to the -base of transistor 45 to keep this transistor strongly conducting so that the output is held near -12 volts. Under fully loaded conditions, as maximum current iiows in the external load, the output in the line 48 may rise to l0 volts.

Assuming the worst condition during the positive charging portion of the rst large positive peak, point B will be slightly higher than A since less current flows in diode 33 than in diode 34; thus cutol of transistor 37 is assured. As the peak is reached, the voltage conditions reverse, since diode 34 is now conducting more current than diode 33; and as the peak is passed, diode 33 is reversely polarized, point B drops below A and transistor 37 conducts. As a result, points C and D are driven rapidly to -6 volts while point C continues to rise slightly above point D as current flows from capacitor 32 through transistor 37 and the series limiting resistor 318 to the base of transistor 40. This causes a sharp drop in voltage at point E from +6 to -6 volts. This transient is conducted by capacitor 42 to point F which drops sharply from -10 vOlts to about -20 volts cutting off previously conducting transistor 45. The resultant positive rise at the output s coupled back through 20K resistor 51 to point D to assure that transistor 40 will remain conducting throughout the full duration of the output pulse. The duration is determined by the RC product of capacitor 42', the 20K resistor 51 and the setting of potentiometer 44. The pulse width, for the components shown in the network, may be varied from psec. to 450 psec.

In general, the termination of the pulse will not cut off the transistor 40, since the negative slope may still keep transistor 37 on, and transistor 40 will st'ay on until the valley is reached after pulse termination. As this point, transistor 30 again begins to charge capacitor 32, transistor 37 cuts olf and 4points C and D drop to cut otf transistor 40. Point E now rises to +6 volts, charging capacitor 42 in preparation for the next pulse output, This pulse marks the presence of the most prominent harmonic in the complex speech waveform and its position in time. Separatecodes are produced for voiced sounds and this includes vowels and the voiced consonants such as V, Z, etc. Consonants that are unvoiced are not coded by the harmonic locator, these portions of the spoken word being accommodated in the manner described in a co-pending application Ser. No.`474,230, -tiled July 23, 1965 (now Patent No. 3,395,249).

Envelope peak detector The envelope peak detector EPD, shown in FIG. 5, comprises essentially three transistors 75, 78 and 82 connected in the manner shown. The incoming signal line 25 is connected by way of a capacitor 70 to a divider network 71 including, among other components, diodes 72 and 73. Input to the base of transistor 75 from the network 71 is by way of a line 74, and input to the base of transistor 78 is by way of a line 77. The emitters of the transistors 75 and 78 are connected each to a +6 volt supply. Output from the collector of transistor 75 is fed to an output line 83 by way of lines 76 and 84. The collector of transistor 78 is connected by way of line 79 to a +12 volt supply and also to the base of transistor 82 by way of a line 80 which is resistively coupled by way of line 81 to a l2 volt supply. The transistor 82 has its emitter connected to a +6 volt supply and the output of the collector is connected to the output line 83.

Transistor 75 is utilized to `monitor negative peaks arising during negative voltage excursions of the signals appearingin the network 71, and provides positive lsignals, throughinversion, on the output line 83', by way of lines 76 and l84.

The transistors 78 and 82 monitor the positive peaks, arising during positive lexcursions, which are impressed on the output line 83. These positive peak voltages thus provide the fundamental frequency which is utilized to control operations of the scan ring SCR and the time base ring TBIR.

Transistors 85 and 94 are utilized for the AGC function. Transistor 85 integrates the fundamental frequency by way of the line connection 76 to the base thereof to which is also connected an integrating network 86 which includes a capacitor 86a` and a resistor 86r connected to a +6 volt supply. The lopposite end of the network 86 is connected to a 6 volt supply, a line 87 including an AGC indicator which terminates at aA +6 volt supply, and lfinally to the collector of transistor 85. The emitter of transistor 85 along with the emitter of transistor 91 are connected by a line 90 in turn resistively coupled to a -6 volt supply. The collector output of transistor 91 is tapped to a +12 volt supply by way of line 92 and to an output line 93 in turn connected to the line 26. The base of transistor 91 is controlled by a' potentiometer 94 also coupled to the line 93 by way of a capacitor 95. The transistors 85 and'91 function primarily as an amplier by which balanced integration is achieved to obtain the proper AGC range to control the pre-amplifier output signals.

Latch ML The storage matrix SM is constituted of latches ML, MLq ML56, a typical one being shown in FIG. 8. Each latch comprises an input coincidence `network 150` connected by `way of a line 151 to thebase of transistor .152 whose emitter terminates at a -6 volt supply, and the collector is resistively coupled to a +6 volt supply. The collector output is resistively coupled by way of line 153 to the base of transistor 154 whose collector is resistively coupled by way of line 15-5 to the base of transistor 152. A latch indicator 157 is also connected to the collector of transistor i154 by way of the line 156. The emitter of transistor 154 is connected by way of line 158 to a reset line RST.

In the operation of the latch both transistors 152 and 1-54 are cut off following the application of a reset signal on the line 158. The base of transistor 152 is held below -6 volts by the output from the collector of transistor 154. The latter is held olf by a line 153 connected to the collector of transistor 152 which is near +6 volts. If both inputs to the ANID circuit are near -12 volts, the base of transistor 152y is also near 12 volts. With one input at +12 volts and one at ground, the latch is maintained at cutoff.

When both inputs are raised to about ground (0 volt), current ows in the base of transistor 152 to turn the latter on. The collector drops and turns on transistor 154 which raises its collector to near ground to cause the indicator lamp to light. The resistive path 155 enables sucient base current to flow to keep transistor 154 on, even though both inputs should drop to -12 volts. The isolating input diode 151 is backbiased for this condition so that base current does not ow away from the base of transistor 152. Thus, the latch will stay on until reset.

Adjustable delay The adjustable delay AD is shown in FIG. 9 and comprises a network which includes tive transistors, namely 168, -171, 177, 180 and 183, and an adjustable RC network 173. Incoming signal excursions of approximately 12 volts are presented to an input divider network 166 through a line 167 to the base of transistor 168 which is further coupled to transistor 171 by -way of circuit paths and 172. Path 170 interconnects the collector of transistor -168 to the base of transistor 171 and the path 172 includes a capacitor 173a and interconnects the emitters of transistors 168 and 171. The emitter of transistor 171 isv connected to the base of transistor 177 by way of a line 174 to which is also tapped the network 173 which includes line 175 and a potentiometer 176. The emitter of transistor I177 is resistively connected to a -12 volt supply by way of a line 178 and also interconnects the base of transistor 180 by way of a resistive line 179. The collector output of transistor 180 extends to a +6 volt supply by way of a resistive line 181 and interconnects the base of transistor 18.3 by way of a resistive path 182. The collector of transistor 183 is resistively connected to a -12 volt supply and the collector output is impressed on output line 184.

In operation, when the incoming signal level drops from zero volts to -12 volts, transistor 168 conducts and charges capacitor 173a which forms a part of the network 173. The charging of the capacitor causes a delayed rise lfrom 12 volts to -6 voltsv at the emitter output of transistor 171. This delayed rise is passed on through the emitter follower transistor 177 and, in combination with transistors 180 and 183, provides a delayed square `wave output on the line 184. This delayed square wave output is utilized to complete the scan signal of the scan ring SCR by storing the end of the S8 pulse from the last stage of the ring for a period of about 3 ms. before turning on the initial stage S41. This delays the turning off of the gated multivibrator GMV and also prevents spurious ring starts which would be occasioned by noise transients passing through the envelope peak detector EPD.

Gated multivibrator The gated multivibrator GMV shown in FIG. 10i comprises essentially three transistors 192, .194, 203, an RC network, a rate control potentiometer 200, all of which are connected in the manner shown. Incoming gating signals are fed across a gating resistor through line 191 to the base of transistor 192 whose emitter is interconnected with the emitter of transistor 194 by way of line 197 which is connected to a -6 volt supply. The collectors of transistors 192 and 194 are resistively intercoupled by way of line 193 also connected to a +6 volt supply. The collector of 194 is cross coupled to the base of transistor 192 by way of a line 196 and a charging capacitor 195. The collector of transistor 192 is resistively coupled by way of line 202 to transistor 203 and capacitively coupled to the base of transistor 194. Also connected to the base of transistor 194 is an RC network 198 which includes a capacitor 201, resistor 199 and the rate control potentiometer 200. The emitter of transistor 203 is grounded and the collector is resistively coupled to a -12 volt supply by way of a line 204. The collector output passes through output line 205.

In the operation of the multivibrator GMV, a gate signal, when raised from a -12 volt level to ground, is passed through the gating resistor 190 to charge capacitor 195 and after a brief delay, depending upon the time constant of this RC combination, the transistor 192 is driven into conduction and the transistor 194 is cut off, as a result of which transistor 203 is driven into conduction to provide an output on the line 205. Multivibrator action continues between the transistors 192 and 194 as each alternately conducts and the action continues so long as the input gate signal is up; dropping this gate signal to -12 volts terminates the multivibrator action. The frequency of the multivibrator action is under the control of the RC network 198 and the setting of the rate control potentiometer 200.

Ring drive The ring drive RD, shown in FIG. 11, comprises transistors 213, 216 and 224 connected in the network shown. Input timing signals enter the ring drive by way of a capacitor 210, line 212 to the base f transistor 213 whose emitter is connected to a16 volt supply, and the collector to +6 volts by way of a resistor 217. Transistor 216 has its base connected to the collector of transistor 213 by way of a coupling capacitor 219 and also to ground by way of a 10K resistor 220. The collector output of transistor 213 is fed into the base of transistor 224 by way of a line 221 and a resistor 222. A +12 volt supply is connected to the base of transistor 224 by way of resistor 223. The emitter of transistor 224 is resistively connected to a +6 volt supply and the collector to a -6 volt supply. The collector is clamped to ground by the diode. The collector output is passed on to line 226 which is connected to the open ring drive line 505, in the case of driver RD2, and line 83 in the case of RDl.

In operation, the signals enter the ring drive by way of the capacitor 210. Transistors 213 and 216, in conjunction with the capacitor 219 and resistor 220, function as a pulse generator to produce pulses of definite length, the length being dependent upon the time constant of the resistor 220 and the capacitor 219. The purpose of the transistor 224 is to provide drive as well as a shift in the pulse level. The output pulse from the instant circuit varies between ground and +6 volts and has a pulse period of approximately 130 psec. The ring drive associated with the time base ring in FIG. 2f is referenced RD3.

An OR configuration 260 is shown in FIG. 13. The presence of a signal on either or both of two inputs 261 and 262 provides an output on line 263.

A delay switch DS shown in FIG. 15 comprises a transistor 280 having a grounded emitter and an RC network 281 connected to the base of transistor 280. The RC network includes a capacitor 282 and resistor 284:1. A relay coil 28.5 is connected from 12 volts to the collector of transistor 280. A power tum-on switch PSW is interposed between the capacitor 282 and a power supply which supplies appropriate voltages to provide a time delay of at least a second or more. The PSW switch, when closed, causes the coil 285 to energize and close associated contacts 285 following a delay determined by the time constant of the delay switch. This provides an output to reset the matrix latches by way of reset line RST.

Inverter The inverter 370 (INV) is used to produce a complement or inverted output which has the opposite condition to the input. Referring to FIG. 14, when the input is ON, at 0 volt, the output is OFF at -12 volts, and when the input is OFF, at -12 volts, the output is ON at 0 volt. The input signal is applied to terminal 371. When the signal is at 0 volt, current flows from +6 volts through resistors 373 and 372 in series to terminal 371 at 0 volt, so that the base of PNP transistor 375 connected to the junction of the resistors will be at a voltage higher than 0 volt and the transistor is cut off. With this input condition, no current flows in line 376 to resistor 377 and terminal 378 will be at l2 volts for the no-load condition.

`On the other hand, when the input signal is at -12 volts, the line 374 would be well below 0 volt were it not for current iiowing from ground through the emitter and the base of transistor 375. This current puts the transistor into heavy conduction and the output terminal is raised to 0 volt as current flows from line 376 to the load and through resistor 377 to -12 volts.

Ring units The ring unit, shown in FIG. 12, is constituted of a plurality of two-stage units RUO-RU9. A stage is turned on only when the previous stage has been on for some time and a ring drive pulse turns the stage on with no overriding conditions or pulse races. D.C. feedback is used to turn olf the preceding stage. The ring is immune to noise and responds well to start-stop operation.

Two ring positions are shown so that an explanation of the relation of one unit to the other may be facilitated.

During a reset, all units are turned off so that the outputs 499, 516, etc., are at or near -12 volts. It will then be required to set one position, usually the lirst stage, to an ON state. This may be done immediately after the resetting operation or at a later time. This unit has been designed so that a negative pulse, from 0 to -12 volts, performs the RESET operation and the end of the pulse may be used to SET stage 1 ON. When the input signal at terminal 470 goes negative, from 0 volt to -12 volts, junction 472 is driven below the 12 volts potential, the initial value due to the effects of resistor 473. During the negative pulse, however, it is -quickly restored to -12 volts by current tiowing in diode 477 through junction 476, resistor 474 to junction 472. When the SET input 470 rises from l2 to 0 volt, junction 472 is driven positive from -12 volts to about 0 volt. Current now ows from junction 472 through resistor 474 to junction 476 and thence through diode 475, junction 478, and line 479 to the base of transistor 480. Current also flows through resistor 481 to junction 482 which is held at nearly -12 volts by conduction through transistor 484. The current owing from junction 482 to the -12 volt supply proceeds along two paths. One path extends from junction 482 through the emitter-base diode of transistor 484 to junction 486 through resistor 487 to the +12 volt supply. The other path extends through junction 482 through the conducting PNP transistor 484 through resistor 488 to the -12 volt supply. When junction 478 reaches about -6 volts, current begins to ow in the base-emitter diode of transistor 480 to -6 Volts to turn the transistor on and cause current to flow from +6 volt supply through resistor 489, through junction 490, resistor 491, junction 492, resistor 493, conducting transistor 480 to the -6 volt supply. The drop across resistor 489 causes junction 490 to drop below O volt, whereupon current ows from Reset line 495 to junction 496, line 497 to the emitter of transistor 485, the emitter-base diode of the transistor, junction 490, resistor 491, junction 492, resistor 493,

transistor 480 to the -6 volt supply. This causes transistor 485 to conduct current flow from the Reset line 495 through junction 496, line 497, conducting transistor 485, line 486', terminal 486, resistor 487 to the -12 volt supply. The drop across resistor 487 causes junction 486 connected to the base of transistor 484 to rise above its emitter connected to junction 482 to cut off the transistor so that it will not resist the drive-on action of transistor 485. Current flow from the transistor passes through diode 483 to raise junction 482 and output terminal 499 to near zero volts. Current also flows through resistor 481 to the base of transistor 480 to keep the latter conducting. This, in turn, keeps transistor 485 conducting so that the ring stage one is latched ON, the drop across conducting diode 483 assuring that junction 486 remains at a higher potential than junction 482 to maintain transistor 484 in a cutoff state.

Since the output terminal 499 has now risen to volt, a gating action takes place for the second ring stage to cause current flow through resistor 501 to junction 502, capacitor 503, line 504 to ring drive line 505. This charges capacitor 503 until the voltage at junction 502 rises to about -8 volts. At this time the current flowing away from junction 502 through diode 508, the base of transistor 509, resistor 510 to junction 511, conducting transistor 512, resistor 513 to a -12 volt supply, equals the current flowing into junction 502 from the output line 499 through resistor 501. Thus, a state 4of equilibrium exists with transistor 509 at cutoff, so that position 2 is still off, even though gated by position 1.

When a positive going ring drive pulse appears on the line 505, a turn-.on action is transmitted by way of line 504 through capacitor 503 to junction 502. which attempts to rise above -6` volts from the original 8 volt level. As junction 502 reaches -6 volts, current flows in diode 508 to the base-ernitter diode of transistor 509 turning it on. As a result, the positive bias on transistor 515 is removed by current flowing into conducting transistor 509 through resistors 519, 521 and 523. When transistor 515 conducts, a positive bias is applied to transistor 512, cutting the later olf so that it raises junction 511 and output line 499 from near -12 volts to 0 volt. Current ilowing from junction 511 through resistor 510 maintains transistor 509 in conduction and also keeps transistor 515 on, so that ring stage 2 is latched on.

The rise at output line 516 is conducted via line 517 back to diode 518 which conducts and raises junction 492 to near 0 volt even though transistor 480 is conducting inasmuch as a voltage drop .of about 6 volts builds up across resistor 493. When junction 492 rises, current is reduced in the resistors 521 and 519 so that junction 520 rises above ground (0 volt) and transistor 485 cuts off. This drops junction 482 and .output line 499 and places a negative bias on the base of transistor 480 through resistor 481. Thus, transistors 485 and 480 resume their cutoff states and transistor 484 reverts to conduction. Base current now `flows in transistor 484 from junction 482 to the emitter-base diode of transistor 484, junction 486, and through resistor 487 to the -12 volt supply. This causes an amplified current to flow from output line 499 through junction 482 to conducting transistor 484, resistor 488, to the -12 volt supply to maintain the output line 499 at its off level.

The rise at output line 516 will gate on ring stage 3 so that the following ring drive pulse will energize stage 3, whereupon transistor 515 turns off through diode 518 in the manner described for stage 1. Thus each unit gates on the succeeding unit, which comes on with the occurrence of a ring drive pulse and turns off the preceeding stage via the feedback connection.

In the case of a closed ring, the final stage output becomes the input gate for stage 1. The rise at the input line 525 causes current to iiow through resistor 526 to junction 527 to charge capacitor 528. The next ring drive pulse on line 505 is passed by capacitor 528 to junction 527 to turn on transistor 480 as current flows through diode 529 to junction 478 to the base of transistor 480. Thus, a new ring cycle is started and the ring stages will turn on and olf in succession in the manner described.

Scan counter The scan counter, shown in FIG. 16, is used to count the output pulses from the harmonic locator during a given scan interval. During scanning, the scan ring generates successive pulses on the input diode 301a and the harmonic locator provides pulses to input diode 301b. The NPN transistor 304 is normally biased off as the base 304b is held below the -6 volt reference atl the emitter 304e by current flowing in either input diode. When a coincidence of positive pulses occurs at the inputs, both diodes are backbiased and current ows from the +12 volt supply through resistor 302 into the base 304b and thence to the emitter 304e and the -6 volt supply. This causes transistor 304 to conduct and current ilows from the |6 volt supply through resistors 306iand 305, lowering the potential at intersection 307 until PNP transistor 308 conducts. The result of the double inversion is a well-shaped squarewave pulse on line 310 from -6 volts to 0 volt. Line 310 is clamped to -6 volts by diode 311 as current normally flows from -6 volts through diode 311 to line 310 and through resistor 309 to -12 volts. When transistor 308 conducts, line 310 rises sharply to 0` volt, reversely biasing diode 311. At the end of the input coincidence, NPN transistor 304 cuts off as one or both inputs drop to an off level below -6 volts. The resultant positive rise at junction 307 cuts off PNP transistor 308 as the base 30811 rises above the emitter 308e which is referenced to ground. Line 310 then falls to -6 volts where it is held by clamp diode 311.

The six volt positive pulses formed by the double inversion of the input coincidence are coupled to intersection 313 by capacitor 312. This is the input to a welland-bucket circuit, well known in the art, wherein increments of charge on a small capacitor are transferred to a larger capacitor so that a counting effect is achieved. In this circuit, the charge on capacitor 312 is conducted through diode 316 to one side of capacitor 318, the other side of 318 being referenced to ground potential. The transfer of charge takes place on the positive transient and when the negative transient from 0 to -6 Volts occurs on line 310, intersection 313 tries to fall, but this is prevented by current flowing through diode 314 from the output terminal 355. This terminal had just risen by one incremental step by reason of increased conduction in transistors 322 and 325. The small step in voltage at intersection 317 causes a small increase in current flowing from ground through resistor 323 :and transistor 322 to the base of transistor 325 which in turn increases the current flowing from ground through resistor 324 and transistor 325. Thus the drop across resistor 327 increases by essentially the same amount as the increase in voltage on capacitor 318 and the junction 326 and the rise on output line 355. This in turn causes intersection 313 to be held to a voltage higher than before the input pulse began. The next input pulse drives the same amount of current as before through diode 316 as the incremental charge on capacitor 312 transfers to capacitor 318. Each input coincidence raises the output terminal through about 0.15 volt. After 20 pulses the output rises about 3.0 volts, and after 30 pulses about 4.5 volts, and so on. When the output has been utilized, the counter is reset. A pulse applied through resistor 321 causes NPN transistor 329 to conduct as current ows through the limiting resistor 321 to the base 320b and out of 320e to the 6 volt supply. This causes heavy current to ow in resistor 319 to quickly discharge capacitor 318 and prepare the Scan Counter for a new counting cycle. 

